Browse Problems

A Single Wire

Four Independent Wires

Inverter (NOT Gate)

2-Input AND Gate

Output Zero

Constant One Output

Constant Vector Output

2-to-1 Multiplexer

Half Adder

Full Adder

NOR Gate

XNOR Gate

Declaring Wires

7458 Chip

Vectors

8-bit Vector Bit Reversal

Byte Select from a 32-bit Word

Concatenation and Replication

Sign Extension

Four-Input Gates

Vector Bitwise and Logical Operators

Vector Part Select

Vector Reversal

Vector Concatenation and Splitting

Replication Operator

Vectors in More Detail

More Replication: Pairwise Equality

Instantiate a Submodule by Name

Modules

Connecting Ports by Position

Instantiate Multiple Copies of a Submodule

Connecting Ports by Name

Connecting Submodules with an Intermediate Wire

4-bit Ripple-Carry Adder from Full Adders

Combining Two Different Submodule Types

Three Modules

Modules and Vectors

Adder 1

Adder 2

Carry-Select Adder

Adder-Subtractor

Always Blocks: Combinational

Priority Encoder (if/else)

3-to-8 Decoder (case statement)

Always Blocks: Clocked

Population Count (for loop)

Min/Max of Four Values

If Statement: Conditional Selection

Transparent Latch

Case-Based Multiplexer

Priority Encoder with Wildcards

Complete Combinational Decode

If Statement: Avoiding Latches

4-to-1 Mux with the Ternary Operator

Parity Generator (reduction operators)

Parameterized XOR Ring (generate)

Wide Reduction Gates

100-Bit Ripple-Carry Adder with Carry Outputs

Generated BCD Adder

100-Digit BCD Ripple-Carry Adder

100-Bit Vector Reversal

255-Bit Population Count

Wire

2-to-1 Multiplexer (Gate-Level)

Ground

4-to-1 Multiplexer

BCD to 7-Segment Display Decoder

NOR

Another Gate

4-bit Priority Encoder

Karnaugh Map Function

Two Gates

8-bit Magnitude Comparator

More Logic Gates

7420 Chip

4-bit Barrel Shifter (Rotate Left)

Two-Bit Equality

Simple Circuit A

Simple Circuit B

Combine Two Circuits

Ring or Vibrate?

Thermostat

3-Bit Population Count

2-to-1 Bus Multiplexer

9-to-1 Multiplexer

256-to-1 Multiplexer

256-to-1 4-Bit Multiplexer

3-Bit Binary Adder

32-Bit Adder

Signed Addition Overflow

100-Bit Binary Adder

4-Digit BCD Adder

3-Variable Karnaugh Map

4-Variable Karnaugh Map 1

4-Variable Karnaugh Map 2

4-Variable Karnaugh Map 3

Minimum SOP and POS Forms

K-map Function Using Multiplexers

Truth Tables

Even Longer Vectors

Karnaugh Map with Don’t-Cares

SR Latch (Gate-Level)

D Flip-Flop with Asynchronous Reset

D Flip-Flop with Synchronous Reset and Enable

4-bit Up/Down Counter

Decade (Mod-10) Counter

Four-Bit Loadable Shift Register

Moore FSM: Non-Overlapping Sequence Detector (1011)

Mealy FSM: Overlapping Sequence Detector (1011)

D Flip-Flop

D Flip-Flops

DFF with Synchronous Reset

DFF with Configurable Reset Value

DFF with Byte Enable

D Latch

D Flip-Flop

MUXDFF Primitive

Detect a Rising Edge

Detect Both Edges

Edge Capture Register

Dual-Edge Register

Counter 1 to 12

Counter 1000

Slow Decade Counter

4-Digit Decimal Counter

12-Hour Clock

Four-Stage Shift Register with Reset

Left/Right Rotator

Arithmetic Shift by 1 or 8

5-Bit LFSR

3-Bit LFSR

32-Bit LFSR

Enabled Shift Register

Bidirectional Shift Register

3-Input Lookup Table

Simple FSM 1 (Asynchronous Reset)

Simple FSM 1 (Synchronous Reset)

Simple FSM 2 (Asynchronous Reset)

Simple FSM 2 (Synchronous Reset)

Simple One-Hot State Transitions

Design a Moore FSM

Simple FSM 3 (Asynchronous Reset)

Simple FSM 3 (Synchronous Reset)

Lemmings 1: Walk

Lemmings 2: Bump

Lemmings 3: Fall

Lemmings 4: Bump and Fall

Simple State Transitions 3

One-Hot FSM

HDLC Bit-Pattern Recognition

Serial Two’s Complementer (Mealy FSM)

Serial Two’s Complementer (Moore FSM)

Serial Receiver

Serial Receiver and Datapath

Serial Receiver with Parity Checking

Q8: Design a Mealy FSM

Q3a: Three-Cycle FSM Pattern Detector

Q3b: FSM from a State Table

Q3c: FSM Output and Next-State Logic

Q6: Six-State Moore FSM

Q6b: Binary Next-State Bit Y2

Q6c: One-Hot Next-State Signals

Q2a: Six-State Moore FSM

Q2b: One-Hot Next-State Equations

Four-Bit Binary Counter

Decade Counter with Enable

Rule 90 Cellular Automaton

Rule 110 Cellular Automaton

Conway's Game of Life 16x16

Q2a: Another FSM

Q2b: Motor-Control FSM

MUXDFF Shift-Register Stage

DFFs and Gates

Create Circuit from Truth Table

Decade Counter Again

PS/2 Packet Parser

PS/2 Packet Parser and 3-Byte Datapath

4-bit ALU

Traffic Light Controller

Simple Datapath: Register File + ALU + Writeback

UART-Lite Transmitter

Three-Request Priority Arbiter

Counter with Period 1000

4-Bit Shift Register and Down Counter

FSM: Sequence 1101 Recognizer

FSM: Enable Shift Register

The Complete Timer

FSM: One-Hot Logic Equations

FSM: The Complete FSM

Identify the Gate

Infer the Counter

Infer the Mux

Infer the Edge Detector

Find the Bug: 2-to-1 Mux

Find the Bug: NAND Gate

Find the Bug: 4-to-1 Mux

Find the Bug: Add/Subtract

Find the Bug: Case Decoder

Combinational Circuit 1

Combinational Circuit 2

Combinational Circuit 3

Combinational Circuit 4

Combinational Circuit 5

Combinational Circuit 6

Sequential Circuit 7

Sequential Circuit 8

Sequential Circuit 9

Sequential Circuit 10

Exhaustively Test a Full Adder

Verify a Counter's Sequence

Verify an FSM's Output Sequence

Verify a Shift Register

Clock

Testbench1

AND Gate

Testbench2

T Flip-Flop

Synchronous FIFO

Asynchronous FIFO (Dual-Clock, Gray-Coded Pointers)

Circular Buffer (Overwrite-on-Full)

FIFO with Almost-Full Flag

FIFO with Almost-Empty Flag

2-Flop Synchronizer

Pulse Synchronizer

Toggle Synchronizer

Handshake Synchronizer (4-Phase Req/Ack)

Valid/Ready Interface Basics

Ready/Valid Pipeline Stage

Skid Buffer

Backpressure-Aware FIFO-Fed Pipeline

2-Stage Pipeline

4-Stage Pipeline

Pipelined Multiplier

Pipelined Adder (Carry-Select, 2-Stage)

Latency Matching with Shift Registers

Synchronous ROM

Single-Port RAM

Dual-Port RAM

Register File (2 Read Ports, 1 Write Port)

External SRAM Controller

CS450 Timer

CS450 Two-Bit Saturating Counter

CS450 Branch History Register

CS450 Gshare Branch Predictor