HDLbits

Verification/Reading Simulations

Sequential Circuit 7

medium
trace-tablesequential

Infer the sequential behavior from the clocked trace table, including which clock edge captures the input and what value is stored.

The following stimulus and observed outputs are a newly prepared trace for this exercise:

clock edge a at edge q after edge
↑ 0 1
↑ 1 0
↑ 0 1
↑ 1 0