HDLbits

Verification/Reading Simulations

Sequential Circuit 8

medium
trace-tablesequential

The trace table exposes both an intermediate output p and a registered output q. Infer the storage behavior of each from how they respond to clock and a.

The following stimulus and observed outputs are a newly prepared trace for this exercise:

event clock a p after event q after event
initial 0 0 0 0
clock rises 1 1 1 0
a changes while high 1 0 0 0
a changes while high 1 1 1 0
clock falls 0 1 1 1
a changes while low 0 0 1 1
clock rises 1 0 0 1
clock falls 0 0 0 0