Reading Simulations

Identify the Gate

Read a captured input/output table from a simulation and figure out which 2-input gate produced it.

Infer the Counter

Infer a synchronous counter's reset and increment behavior from a recorded cycle-by-cycle sequence.

Infer the Mux

Read an exhaustive input/output table for a three-input circuit and recognize it as a 2-to-1 multiplexer.

Infer the Edge Detector

Infer a rising-edge detector's one-cycle memory from a recorded input/output trace.

Find the Bug: 2-to-1 Mux

Repair a selector whose two data inputs are swapped.

Find the Bug: NAND Gate

Correct an inverted two-input AND function.

Find the Bug: 4-to-1 Mux

Fix a four-way selector with incorrectly decoded select bits.

Find the Bug: Add/Subtract

Implement unsigned add/subtract selected by a control bit.

Find the Bug: Case Decoder

Repair a decoder so each selector value activates the matching one-hot output.

Combinational Circuit 1

Infer the combinational function from the supplied input and output trace table. Reproduce the output for every input combination.

Combinational Circuit 2

Infer the four-input combinational function from the trace table. The output is observed while the inputs exercise the input combinations.

Combinational Circuit 3

Infer the four-input combinational function from the recorded trace table. Implement the observed truth table.

Combinational Circuit 4

Infer the four-input combinational function from the recorded trace table and match its output at each sampled time.

Combinational Circuit 5

The trace table uses four-bit hexadecimal values. Infer how the selector `c` chooses among the data inputs and what value is produced for the remaining selector values.

Combinational Circuit 6

Infer the lookup table from the trace table. `a` is a three-bit address and `q` is a sixteen-bit hexadecimal value.

Sequential Circuit 7

Infer the sequential behavior from the clocked trace table, including which clock edge captures the input and what value is stored.

Sequential Circuit 8

The trace table exposes both an intermediate output `p` and a registered output `q`. Infer the storage behavior of each from how they respond to `clock` and `a`.

Sequential Circuit 9

Infer the counter sequence and the effect of input `a` from the trace table. `q` is a four-bit unsigned value; the counter changes on rising clock edges.

Sequential Circuit 10

The circuit has one flip-flop, whose stored value is visible on `state`. Infer the combinational output and the value captured at each rising clock edge from the trace table.