HDLbits

Circuits/Sequential Logic

Serial Two’s Complementer (Mealy FSM)

medium
fsmserial-arithmeticsequential

Input bits arrive least-significant bit first. In the copy state, pass x through until the first 1 has been copied. Then remain in the invert state and output the inverse of every following bit. Reset with active-high asynchronous areset to start another word.

Example input bits: 0 1 0 1 0. The combinational Mealy output is: 0 1 1 0 1.

Serial Two’s Complementer (Mealy FSM) diagram 1