Sequential Logic

SR Latch (Gate-Level)

Build a cross-coupled NOR SR latch and reason about its set/reset/hold/invalid behavior.

D Flip-Flop with Asynchronous Reset

A D flip-flop that samples d on the rising clock edge, with an asynchronous active-low reset.

D Flip-Flop with Synchronous Reset and Enable

A D flip-flop with a synchronous, active-high reset that takes priority over a clock-enable input.

4-bit Up/Down Counter

A 4-bit counter that increments or decrements each clock, with a synchronous reset and free-running wraparound.

Decade (Mod-10) Counter

A synchronous-reset counter that cycles through 0-9 and wraps back to 0, rather than the full 4-bit range.

Four-Bit Loadable Shift Register

Build the top-level four-bit shift register from four MUXDFF stages. `SW` provides the parallel-load data, `KEY(0)` is the clock, `KEY(1)` enables shifting, `KEY(2)` loads in parallel, and `KEY(3)` supplies the serial input. Drive the stored bits on `LEDR`.

Moore FSM: Non-Overlapping Sequence Detector (1011)

A Moore-style FSM that flags each non-overlapping occurrence of the bit pattern 1011 in a serial input stream.

Mealy FSM: Overlapping Sequence Detector (1011)

A Mealy-style FSM that flags every occurrence of the bit pattern 1011 in a serial input stream, including overlapping matches.

D Flip-Flop

Store one bit on each rising clock edge.

D Flip-Flops

Register an eight-bit vector on the rising clock edge.

DFF with Synchronous Reset

Add a synchronous active-high reset to a D flip-flop.

DFF with Configurable Reset Value

Reset a four-bit register to a specified nonzero value.

DFF with Byte Enable

Update a 32-bit register only when its write enable is asserted.

D Latch

Implement a level-sensitive D latch.

D Flip-Flop

Implement a rising-edge-triggered D flip-flop. Capture `in` on the rising edge of `clk` and drive the stored value on `out`.

MUXDFF Primitive

Implement one flip-flop and its input multiplexer. On a rising edge, capture `r_in` when `L` is high; otherwise capture `q_in`. The supplied diagram shows how three copies are connected in the larger circuit.

Detect a Rising Edge

Convert a sampled low-to-high transition into a one-cycle pulse.

Detect Both Edges

Generate a one-cycle pulse for either sampled signal transition.

Edge Capture Register

Capture data once on a rising capture event and hold the result.

Dual-Edge Register

Capture data on both the rising and falling clock transitions.

Counter 1 to 12

Build a clocked counter cycling through values 1 to 12.

Counter 1000

Count modulo 1000 with a synchronous reset.

Slow Decade Counter

Use a slower enable pulse to advance a decade counter.

4-Digit Decimal Counter

Count from 0000 through 9999 and present the value as packed BCD.

12-Hour Clock

Advance hours, minutes, and seconds in a 12-hour clock.

Four-Stage Shift Register with Reset

Build the four-stage shift register shown. On each rising edge, shift `in` through the four flip-flops toward `out`. `resetn` is a synchronous active-low reset that clears all four stages.

Left/Right Rotator

Rotate an eight-bit value left or right by one bit per cycle.

Arithmetic Shift by 1 or 8

Register a signed value after an arithmetic right shift of one or eight bits.

5-Bit LFSR

Advance a five-bit linear-feedback shift register from a fixed nonzero seed.

3-Bit LFSR

Build a three-bit linear-feedback shift register.

32-Bit LFSR

Advance a 32-bit LFSR using four feedback taps.

Enabled Shift Register

Shift a serial input into a register only on enabled cycles.

Bidirectional Shift Register

Shift an eight-bit register in either direction with a serial input.

3-Input Lookup Table

Use three logic inputs as the address of an eight-bit lookup table.

Simple FSM 1 (Asynchronous Reset)

Implement a two-state Moore machine with an active-high asynchronous reset.

Simple FSM 1 (Synchronous Reset)

Implement a two-state Moore machine with synchronous reset.

Simple FSM 2 (Asynchronous Reset)

Toggle between two states on input events with an asynchronous reset.

Simple FSM 2 (Synchronous Reset)

Toggle between two states on input events with a synchronous reset.

Simple One-Hot State Transitions

Cycle a three-state machine through one-hot encoded states.

Design a Moore FSM

Build a Moore machine that recognizes two consecutive sampled ones.

Simple FSM 3 (Asynchronous Reset)

Build a three-state counter-style FSM with asynchronous reset.

Simple FSM 3 (Synchronous Reset)

Build a three-state counter-style FSM with synchronous reset.

Lemmings 1: Walk

Create the walking outputs for a simple two-direction character controller.

Lemmings 2: Bump

Turn the character around when it bumps into either wall.

Lemmings 3: Fall

Track whether the character is walking or falling based on ground support.

Lemmings 4: Bump and Fall

Combine wall collisions and missing ground in a small character controller.

Simple State Transitions 3

Implement a three-state transition graph driven by a serial control input.

One-Hot FSM

Implement a four-state ring machine using one-hot state encoding.

HDLC Bit-Pattern Recognition

Recognize three patterns in a serial input stream. Pulse `disc` for `0111110`, pulse `flag` for `01111110`, and assert `err` for seven or more consecutive 1s following a 0. Each output is a Moore-style indication for one cycle, except `err` remains asserted while the run of 1s continues. Reset must behave as though the previous input bit was 0.

Serial Two’s Complementer (Mealy FSM)

A one-hot Mealy serial two’s-complementer with asynchronous active-high reset.

Serial Two’s Complementer (Moore FSM)

A Moore-style, least-significant-bit-first serial two’s-complementer with asynchronous active-high reset.

Serial Receiver

Receive a start bit, eight data bits, and a stop bit using a sample enable.

Serial Receiver and Datapath

Coordinate serial frame timing and byte capture in a receiver.

Serial Receiver with Parity Checking

Check odd parity while receiving serial data frames.

Q8: Design a Mealy FSM

Recognize an overlapping 1101 pattern with an output pulse on its final input bit.

Q3a: Three-Cycle FSM Pattern Detector

Start the circuit when `s` is asserted while reset state A is active. Then examine `w` in non-overlapping groups of three clock cycles. Set `z` during the cycle after a group contains exactly two 1s; otherwise keep `z` low. Continue processing groups until reset.

Q3b: FSM from a State Table

Implement the synchronous FSM defined by the complete state-assigned table.

Q3c: FSM Output and Next-State Logic

Derive Y0 and z from the state table, including defined outputs for each used state.

Q6: Six-State Moore FSM

Complete the six-state synchronous-reset Moore FSM from the provided diagram.

Q6b: Binary Next-State Bit Y2

Derive the binary-encoded next-state bit from the six-state diagram.

Q6c: One-Hot Next-State Signals

Derive two one-hot next-state equations from the six-state diagram.

Q2a: Six-State Moore FSM

Implement the six-state Moore FSM shown. Reset synchronously to A. The output is high only in states E and F.

Q2b: One-Hot Next-State Equations

With one-hot assignment y(5 downto 0) = 000001, 000010, 000100, 001000, 010000, 100000 for states A through F, derive Y1 and Y3.

Four-Bit Binary Counter

Build a four-bit modulo-16 binary counter.

Decade Counter with Enable

Add a count enable to a modulo-10 counter.

Rule 90 Cellular Automaton

Update a one-dimensional cellular automaton using Rule 90.

Rule 110 Cellular Automaton

Implement a one-dimensional cellular automaton with Rule 110.

Conway's Game of Life 16x16

Compute a 16 by 16 Game of Life generation with dead cells beyond the boundary.

Q2a: Another FSM

Detect a run of three consecutive high input samples.

Q2b: Motor-Control FSM

A synchronous FSM that pulses f, detects the serial sequence 101, then latches the result of a two-cycle y check into g.

MUXDFF Shift-Register Stage

Implement one stage of the shift register. On each rising edge, load `R` when `L` is high; otherwise load the serial/neighbor input `w` when `E` is high; otherwise hold the current value `Q`.

DFFs and Gates

Compute a bitwise gate function and register its result.

Create Circuit from Truth Table

Implement a sequential transition table as a clocked circuit.

Decade Counter Again

Add a synchronous load path to a decade counter.

PS/2 Packet Parser

Recognize three-byte PS/2 packets in a continuous byte stream.

PS/2 Packet Parser and 3-Byte Datapath

Find three-byte PS/2 message boundaries and capture each completed packet.