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Circuits/Sequential Logic

Four-Bit Loadable Shift Register

medium
shift-registeruniversalsequential

Build the top-level four-bit shift register from four MUXDFF stages. SW provides the parallel-load data, KEY(0) is the clock, KEY(1) enables shifting, KEY(2) loads in parallel, and KEY(3) supplies the serial input. Drive the stored bits on LEDR.

Four-Bit Loadable Shift Register diagram 1