HDLbits

Circuits/Sequential Logic

HDLC Bit-Pattern Recognition

medium
fsmsequence-detectorsequential

Recognize three patterns in a serial input stream. Pulse disc for 0111110, pulse flag for 01111110, and assert err for seven or more consecutive 1s following a 0. Each output is a Moore-style indication for one cycle, except err remains asserted while the run of 1s continues. Reset must behave as though the previous input bit was 0.

HDLC Bit-Pattern Recognition diagram 1