Build a single D flip-flop with an asynchronous, active-low reset. When active-low ar is low, q must go to 0 immediately — independent of clk. When ar is high, q follows d, sampled on each rising edge of clk.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising-edge triggered |
ar |
input | 1 | Asynchronous, active-low reset |
d |
input | 1 | Data input |
q |
output | 1 | Registered output |
Behavior
- When
arfalls low,qis forced to0right away (not synchronized toclk). - Otherwise, on each rising edge of
clk,q <= d.
